UMC-江苏珞珈聚芯集成电路设计有限公司

Foundry

UMC工艺列表，列表中没有的工艺请电话咨询！

CIS180 Image Sensor 1.8V/3.3V 2P4M

0.18 µm CMOS Image Sensor 1.8 V/3.3 V 2P4M Metal Metal Capacitor Process Design Support

Technology characteristics	Shrink technology: NO Core voltage: 1.8V I/O voltage: 3.3V Shallow Trench Isolation (STI) Twin well Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate RVt, 1.8V LVt N/PMOS, 3.3V LVt N/PMOS, Zero-Vt NMOS Temperature range: -40C to 125C # of metals: 4 Interconnect material: Al Dielectric: FSG Top metal: 5KA Inductors MiM: 1fF/µm² Poly/Poly capacitor: 3 fF/µm² Passivation: single
Wafer size	8 inch
Deliverables	# of dies: 50 for an MPW, 25 for a mini@sic run
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Mentor Graphics, Synopsys
P&R tools	Cadence, Synopsys
Foundry IP	Faraday standard cell libraries Faraday I/O library 3.3V Faraday memories
MPW block size	5mm x 5mm

L180 EFLASH/EE2PROM

UMC 0.18 µm 1.8V/3.3V 1P6M logic process with embedded Flash/EEPROM memories

Technology characteristics	Shrink technology: NO Core voltage: 1.8V I/O voltage: 3.3V Shallow Trench Isolation (STI) Triple well Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate Std Vt, 3.3V LVt PMOS, 3.3V LVt NMOS, 1.8V LVt PMOS, 1.8V LVt NMOS, 3.3V zero_Vt NMOS, 14V HV, 6.5V MV Temperature range: -40C to 125C # of metals: 6 Interconnect material: Al Dielectric: FSG Top metal: 8KA, 12 KA Inductors MoM MiM: 1fF/µm² Passivation: single
Wafer size	8 inch
Deliverables	# of dies: 50 for an MPW, 25 for a mini@sic run
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Mentor Graphics, Synopsys
P&R tools	Cadence, Synopsys
Foundry IP	Faraday standard cell libraries Faraday I/O library 3.3V Faraday memories
MPW block size	5mm x 5mm

L180 Mixed Mode/RF 1.8V/3.3V 1P6M

UMC L180 MM/RF 1.8V/3.3V 1P6M technology

Technology characteristics	Shrink technology: NO Core voltage: 1.8V I/O voltage: 3.eV Shallow Trench Isolation (STI) Triple well Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate Std Vt, 3.3V LVt PMOS, 3.3V LVt NMOS, 1.8V LVt PMOS, 1.8V LVt NMOS, 3.3V zero_Vt NMOS Temperature range: -40C to 125C # of metals: 6 Interconnect material: Al Dielectric: FSG Top metal: 8KA, 12 KA or 20KA Inductors MoM MiM: 1fF/µm² Passivation: single
Options that need special attention	OTP
Wafer size	8 inch
Deliverables	# of dies: 50 for an MPW, 25 for a mini@sic run
Design tools	Cadence CDBA, Cadence OA, Laker, Mentor, Tanner, ADS
Simulation tools	eldo, hspice, spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Mentor Graphics, Synopsys
P&R tools	Cadence, Synopsys
Foundry IP	Faraday standard cell libraries Faraday I/O library 3.3V Faraday memories
MPW block size	5mm x 5mm

L130 Logic/Mixed-Mode/RF

0.13 µm Mixed-Mode and RFCMOS 1P8M Metal Metal Capacitor FSG Enhancement Process

Technology characteristics	Shrink technology: NO Core voltage1.2V I/O voltage 2.5V or 3.3V Shallow Trench Isolation (STI) Twin and triple well Substrate resistivity 15~25 ohm.cm on <100> P- substrate HS, LL, SP, HS_SP, HS_LL, SP_LL, HS Native Vt, SP Native Vt Temperature range -40C to 125C # of metals: 5 to 8 Interconnect material: Cu Dielectric: FSG Top metal: 8KA, 20KA Inductors MoM MiM: 1fF/µm² or 1.5fF/µm², mutual exclusive Passivation: single
Wafer size	12 inch
Deliverables	90 dies / wafer on MPW, 45 dies / wafer on mini@sic
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Mentor Graphics, Synopsys
P&R tools	Cadence, Synopsys
Foundry IP	Standard cells I/O library: NA
MPW block size	5mm x 5mm

L110AE Logic/Mixed-Mode/RF

0.11 µm Logic and Mixed-Mode 1P8M Metal Metal Capacitor Al Advanced Enhancement Process.

Technology characteristics	Shrink technology: YES Core voltage: 1.2V I/O voltage: 1.8V/2.5V/3.3V/5V Shallow Trench Isolation (STI) Triple well Substrate resistivity 15~25 ohm.cm on <100> P- substrate Vt options: HS, SP, LL, HS_SP, HS_LL, SP_LL and HS_SP_LL Temperature range: -40C~125C # of metals: 8 Interconnect material: AlCu Dielectric: USG Top metal: 20KA or 40KA Inductors MoM MiM: 1.0fF/µm² or 1.5fF/µm² or 2.0fF/µm² Passivation: single
Wafer size	8 inch
Deliverables	# of dies (no wafer!): 50 on an MPW, 25 on a mini@sic
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Mentor Graphics, Synopsys
P&R tools	Cadence, Synopsys
Foundry IP	Gate density I/O voltage, OD, UD RAM/ROM/Dual port/register files)
MPW block size	5mm x 5mm

L65N Logic/Mixed-Mode/RF – Standard Performance

65 nm Logic and Mixed-Mode Standard Performance Low-K Process

Technology characteristics	Shrink technology: NO Core voltage1.0V, 1.1V I/O voltage 1.8V, 2.5V, 2.5_OD3.3V, 3.3V MOAT Twin and triple well Substrate resistivity 7~17 ohm.cm on Epi - substrate SP_RVT, SP_HVT, SP_LVT Temperature range -40C to 125C # of metals: 10 Interconnect material: Cu Interconnect dielectric: FSG Top metal: 8kA, 32.5kA RDL: 12kA, 25kA, 36kA Inductors MoM MiM: 2fF/µm² Passivation: single
Wafer size	12 inch
Deliverables	90 samples
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Synopsys, Mentor Graphics
P&R tools	Cadence, Synopsys
Foundry IP	Standard cells I/O library: NA
Dummy filling	by Foundry
MPW block size	4000µm x 4000µm

L65N Logic/Mixed-Mode/RF – Low Leakage

65 nm Logic and Mixed-Mode Low Leakage Low-K Process

Technology characteristics	Shrink technology: NO Core voltage1.2V I/O voltage 1.8V, 2.5V, 3.3V overdrive MOAT Twin and triple well Substrate resistivity 7~17 ohm.cm on Epi- substrate LL_RVT, LL_HVT, LL_LVT Temperature range -40C to 125C # of metals: 10 Interconnect material: Cu Interconnect dielectric: FSG Top metal: 8kA, 32.5kA RDL: 32.5kA Inductors MoM MiM: 2fF/µm² Passivation: single
Wafer size	12 inch
Deliverables	90 samples
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Synopsys, Mentor Graphics
P&R tools	Cadence, Synopsys
Foundry IP	Standard cells I/O library: NA
MPW block size	4mm x 4mm

40N Logic/Mixed-Mode – Low Power

40 nm Logic and Mixed-Mode Low Power Process

Technology characteristics	Shrink technology: NO Core voltage 0.9V I/O voltage 1.8V, 2.5V MOAT Twin and triple well Substrate resistivity 10~15 ohm.cm on Epi- substrate LP_RVT, LP_HVT, LP_LVT, LP_UHVT Temperature range -40C to 125C # of metals: 10 Interconnect material: Cu Interconnect dielectric: FSG Top metal: 8kA, 12kA, 32.5kA RDL: 12.5kA, 34kA MoM MiM: 2fF/µm² Passivation: single
Wafer size	12 inch
Deliverables	90 samples
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Synopsys, Mentor Graphics
P&R tools	Cadence, Synopsys
Foundry IP	Standard cells I/O library: NA
MPW block size	4000µm x 4000µm

28 nm Logic and Mixed-Mode High Performance Compact

28 nm Logic and Mixed-Mode High Performance Compact Process

Technology characteristics	Shrink technology: NO Core voltage 1.0, 1.1V I/O voltage 1.8V, 2.5V MOAT Twin and triple well Substrate resistivity 15~25 ohm.cm on Epi- substrate UHVT, HVT, RVT, LVT, ULVT Temperature range -40C to 125C # of metals: 10 Interconnect material: Cu Dielectric: FSG Top metal: 8kA, 12kA, 32.5kA RDL: 14.5kA, 28kA MoM MiM: 2fF/µm² Passivation: single
Wafer size	12 inch
Deliverables	90 samples
Design tools	Cadence CDBA, Laker
Simulation tools	HSPICE, Eldo, Spectre
Verification tools DRC	Cadence, Mentor Graphics, Synopsys
Verification tools LVS	Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools	Cadence, Synopsys, Mentor Graphics
P&R tools	Cadence, Synopsys
Foundry IP	Standard cells I/O library: NA
Dummy filling	by Foundry
MPW block size	4000µm x 4000µm