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CIS-IS18SI,IL13SI,IL11SI,IL11SJ
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CMOS Image Sensor (CIS) devices play a key role in a wide range of products such as camcorders, digital cameras and mobile phones. CIS devices, which are now available in compact packages that operate on low power, convert real images into electric signals and then into digital signals. We provide various CIS products designed at 0.11um to 0.18um processing nodes. These include CIF, VGA and Megapixel options using N+/PW photo diode, color filters and microlens technologies.
IS18SI
- 3 Level Aluminum Process
- 0.18um Generic Process
- Own Library for 0.18um Compact Process
- Dual Gate Oxide Process
- Pixel & I/O : 3.3V, Core : 1.8V
- Dark Current Reduction Process
- Thin BEOL Height
- Optimized Photo Layers
IL13SI
- 3 Level Aluminum Process
- Low Power Consumption (Low-Leakage) Process
- Own Library for 0.13um Compact Process
- Dual Gate Oxide Process
- Pixel & I/O : 3.3V, Core : 1.5V
- Dark Current Reduction Process
- Thin BEOL Height at Pixel area
- Minimized photo layers
IL11SI
- 3 Level Aluminum Process (4 level metal optional)
- Low Power Consumption (Low-Leakage) Process
- Own Library for 0.11um Compact Process
- Dual Gate Oxide Process
- Pixel & I/O : 3.3V, Core : 1.5V
- Dark Current Reduction Process
- Thin BEOL Height
- Optimized Photo Layers
IL11SJ
- 3 Level Aluminum Process
- M0 local interconnection (only pixel area)
- Low Power Consumption (Low-Leakage) Process
- Own Library for 0.11um Smart Tech. Process
- Dual Gate Oxide Process
- Pixel & I/O : 2.8V, Core : 1.5V
- Dark Current Reduction Process
- Thin BEOL Height
- Optimized Photo Layers
- Option process: 8fF MIM, Optimized Light guide process
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0.18um General Logic,0.18um Analog Specialized,0.11um Digital + Analog
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DB HiTek supports analog IC design with a modular process at the 0.18um node. This process gives customers the flexibility to choose an option that best meets their needs. Our HP180 option, for example, is ideal for implementing high-voltage devices used in high-precision medical or industrial equipment.
0.18um General Logic
- Foundry Compatible DR & Process
- Mass Production over 2M wfs since 2003
- DBH own IPs/Libs
- Available 90% and 85% optical shrink process
0.18um Analog Specialized
- Low Noise with Pure Ox + Buried Channel
- Well Analog Characterized Res. and Cap.
- Good Mismatching
- Available High Voltage (7V ~ 30V)
- HP18 Process Overview
. 0.18um High Precision Analog CMOS
. 1.8V CMOS / 5V CMOS / ~24V DEMOS
. Low Noise Components : Buried Channel PMOS, JFET, BJT
. High Precision Characteristics : Good Si to Model matching, Low mismatching factor, Well characterized Res. & Cap,
Low DA Cap.
. NVM : ~128bit Poly fuse, ~4Kbit EPROM, ~64bit EEPROM
. Digital IP/Lib : 1.8V/5V Std. Cell Lib, IO Lib, and 1.8V Memory Compiler
. SPICE model including Mismatch & Noise, Cadence PDK
0.11um Digital + Analog
- 0.13um channel length with 0.11um shrunk BEOL
- Support Various Vop (1.0, 1.2, 1.5, 2.5, 3.3, 5V)
- ULP (Ultra Low LKG + Low Noise + Low Op.)
- Available RF process with 4um Al Inductor
- TS11 Process Overview
. Optical Shrink Process (90%) of 0.13um Foundry General Process
. eNVM : ~32bit Poly fuse, ~512Kbit EPROM (eMemory), ~128KbitAnti fuse (Kilopass)
. Digital IP/Lib : Multi Vth Std. Cell Lib, IO Lib, Memory Compiler
. SPICE model including Mismatch & Noise, Cadence PDK
- ULP11 Process Overview
. Focus on Low Power + Ultra Low Leakage + Low Power Operation, Able to Minimize both Active Power Consumption
and Leakage in off-status in one technology
. PNO gate oxide is used for lower 1/f noise
. 1.5V Low Power & 1.2V Ultra Low LKG.
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BCDMOS -BD130LV/40V,BD180MV/45V,BD180LV/40V,BD180X/85V,BD350/60V/85V,UHV700V
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BD130LV – 40V Power, 0.13μm BCDMOS
- Foundry compatible 1.5V low power CMOS
- Industry leading NLDMOS and PLDMOS up to 40V
- Implementation of fully Isolated devices is available
- MIM Capacitor, High-Sheet Poly Resistor and Bipolar devices available
- Embedded NVM available
- Standard 1P4M process with up to 8M available
- Fully characterized PDK and industry standard CAD tools are supported
- Thick metal layer or copper plating for power routing
BD180MV – 45V Power, 0.18μm BCDMOS
- Foundry compatible 5V CMOS with gate OX TDDB to be guaranteed up to 6V
- Optionally CMOS can be operated on 6V (or max 6.6V) with larger gate length
- Wide SOA and very low Rsp performance LDMOS up to 45V
- Implementation of fully Isolated devices is available
- MIM Capacitor, High-Sheet Poly Resistor and Bipolar devices available
- Standard 1P4M process with up to 6M available
- Fully characterized PDK and industry standard CAD tools are supported
- Thick metal layer or copper plating for power routing
BD180LV – 40V Power, 0.18μm BCDMOS
- Foundry Compatible 1.8V CMOS
- Industry-leading NLDMOS up to 40V operation
- Implementation of fully Isolated devices is available
- Complementary Drain Extended CMOS (DECMOS) up to 40V operation
- MIM Capacitor and High-Sheet Poly Resistor available
- Embedded NVM available
- Schottky Diode and Bipolar devices available
- Standard 1P4M process, with up to 6M available
- Fully Characterized PDK and Industry Standard CAD Tools Supported
- Thick Metal Layer or Copper Plating for Power Routing
BD180X – 85V Power, 0.18μm BCDMOS
- Foundry Compatible 1.8V CMOS
- IDM-competitive Ron for NLDMOS and PLDMOS up to 85V operation
- Implementation of fully isolated devices is available
- Complementary Drain Extended CMOS (DECMOS) up to 85V operation
- MIM Capacitor and High-Sheet Poly Resistor available
- Embedded NVM
- Schottky Diode and Bipolar devices available
- Standard 1P4M process, with up to 6M available
- Fully Characterized PDK and Industry Standard CAD Tools Supported
- Thick Metal Layer or Copper Plating for Power Routing
BD350 – 60V or 85V Power, 0.35μm BCDMOS
- 3.3V or 5V logic level
- Complementary DEMOS/LDMOS up to 85V operation
- MIM capacitor and high-sheet poly resistor available
- Embedded NVM available
- NPN and PNP bipolar devices available
- Standard 1P3M process, with 4M optional(Thick Al/Thick Cu available)
- Fully characterized PDK and industry-standard tools
Ultra High Voltage BCD process, ‘UHV 700V’
- 0.35μm layout rules and standard 1P2M process, with up to 4M
- 5.5V CMOS
- Fully Scalable 450V/700V nLDMOS (Non-Epi)
- Available single poly process (20V) & double poly process (Vgs=5V, 20V)
- DECMOS, Bipolar and nJFET devices available
- Digital IP / Library set (Std_Cell, EPROM, EEPROM)
- Embedded NVM (EPROM, EEPROM) available without additional mask
